1. Field of the Invention
The present invention relates to generation and distribution of clock signals in a digital system. More particularly, the present invention relates to a digital information processing system with memory modules of a serial bus architecture.
2. Description of the Related Art
Generally, digital systems transfer and receive data signals by putting the data on a bus in synchronization with a clock signal, such that the data is valid on the bus at a time defined by the edge of the clock signal. Since transferring the data as soon as possible is preferable, a highest possible frequency is typically used. The maximum frequency for operation of the clock signal is controlled by three factors: a data set up time relative to the clock signal, a data hold time relative to the clock signal, and a clock skew. The clock skew includes a clock-to-clock skew (i.e., the edge of the clock signal is skewed with respect to the same phase of the clock signal in another portion of the circuit) and a clock-to-data skew (i.e., the edge of the clock signal is skewed with respect to the data on the bus).
In conventional digital systems, it is not normal for many circuit elements to be connected to a single clock signal or for a single driving circuit to drive the clock inputs of all circuit elements. Accordingly, clock buffers for copying the clock signal are typically used to distribute the clock signal to all elements requiring the clock signal. However, the clock buffers generate clock skew. To minimize the clock skew, the clock buffers are typically arranged in a tree-like clock distribution network such that the clock signal supplied to each element passes through an equal number of the clock buffers. Notwithstanding this effort, the skew between the clock buffers may still be present.
FIG. 1 illustrates a block diagram of a conventional information processing system according to the prior art. Referring to FIG. 1, the information processing system 10 includes a chipset (or a memory controller) 12 and Rambus in-line memory modules (RIMM) 14 and 16. The chipset 12 and the memory modules 14 and 16 are connected to a data bus 18, a clock line 20, and a reference voltage line 22. Although the data bus 18 is comprised of a plurality of data lines, for simplicity, it is shown as a single data line. A first termination of the data bus 18 is connected to the chipset 12, and a second termination of the data bus 18 is connected to a termination voltage (Vterm, for instance, 1.8 V) through a termination resistor (Rdata, for instance, 28Ω), which is used as a termination device. A first termination of the reference voltage line 22 is connected to the chipset 12, and a second termination of the reference voltage line 22 is connected to a reference voltage (Vref), which is used as a logic threshold reference voltage of RSL (Rambus signaling level) signal.
A clock generator 24 is connected to a first termination of the clock line 20. The termination voltage (Vterm) is connected to a second termination of the clock line 20 through a termination resistor (Rclk). The clock generator 24 generates a bus clock signal (for instance, 300-400 MHz) used in the chipset 12 and the memory modules 14 and 16. The clock line 20 includes a first and a second clock line segment 20a and 20b, respectively, which are electrically connected to each other at a U-turn (turnaround) point 20c passing through the chipset 12. Each of the clock line segments 20a and 20b has a same length and electrical characteristic as the data bus 18.
When data in the memory modules 14 or 16 is transferred to the chipset 12 as a master (that is, during a read operation wherein the data is transferred to the chipset from the memory modules), the first clock line segment 20a (or a Clock To Master signal (CTM), transferred through the first clock line segment) is used. Alternatively, during a write operation, the data is transferred to memory modules 14 or 16 from the chipset, and a second clock line segment 20b (Clock From Master signal (CFM) transferred through the second clock line segment) is used. A length of the first clock line segment 20a is the length from the clock generator 24 to the chipset 12 (for instance, 2L), a length of the second clock line segment 20b is the length from the chipset 12 to the termination resistor (Rclk) (for instance, 2L), and a length of the data bus 18 is the length from the chipset 12 to the termination resistor (Rdata) (for instance, 2L).
Presently, a serial bus architecture is adapted in the RIMM as a Rambus dynamic random access memory (DRAM) module system. The RIMM may be operated in high frequency since the RIMM can be double-synchronized to the CTM clock signal and the CFM clock signal may serve as the bus clock signal on a same channel. As previously described, the CTM clock signal is an interface clock signal used to transfer Rambus Signaling Levels (RSL) signals to the channel, and the CFM clock signal is an interface clock signal for receiving RSL signals from the channel.
Even though this serial bus architecture is used, the clock signal is skewed as the operation frequency increases due to routing lengths of the clock line 20 and the data bus 18 being different. In the example shown in FIG. 1, the length between the first termination and the second termination of the clock line 20 including the first and the second clock line segments 20a, 20b is 4L, while the length between the first and second terminations of the data bus 18 is 2L. Thus, as the operation frequency increases, the clock signal transferred through the clock line 20 will be more attenuated compared with the data signal transferred through the data bus 18. Also, as the operation frequency increases, a memory device mounted on the memory module 16 farthest from the chipset 12 may not perform an accurate read or write operation due to the attendant skew of the clock signal (i.e., the level of the clock signal is attenuated).